Ferenc Mernyei, Franz Darrer, Matthijs Pardoen, and Andreas Sibrai

Abstract— This letter introduces a new method for reducing the substrate- related losses of integrated spiral inductors for radio frequency (RF) applications. Measurement based equivalent circuit parameters are demonstrated. Using our method the quality factor increased from 5.3 to 6.0 at 3.5 GHz at an 1.8- nH inductor.

Index Terms— Integrated inductor, on- chip spiral, quality factor, substrate loss.

INTRODUCTION

AT SILICON radio frequency (RF) integrated circuits, the usage of on- chip inductors in LC tanks is limited by the achievable quality factor. The modeling of such structures was carefully investigated [1], [2], and the source of losses were described as well [3], [4]. To find the optimal geometry, several “guidelines” were defined [2], [3] and optimizing algorithms were established in computer programs [5]. We can find the optimal line width for the highest possible quality factor for a given size and inductance value at a given frequency, but there have not been any suggestions published yet on how to reduce the substrate- related losses.

REDUCING THE SUBSTRATE LOSSES

By optimizing the spiral geometry, we will end up with a line width which will move the maximum of the curve to the desired frequency. In this case, the ohmic losses and the substrate capacitance will give us the minimal effective resistivity:

                            (1)

The substrate used to be considered a limiting factor that we could not change, or that we had to remove [6].  Since the substrate losses at the silicon substrates are related to its semiconductor nature we cannot easily reduce them. The losses are caused by the eddy currents induced by the magnetic filed of the spirals. The eddy currents are owing around the axis of the spiral. If we can reduce the eddy currents, the quality factor of the spirals will increase. With our BiCMOS technology, most of the substrate currents ow in the top heavily doped p+ layer. This layer can be broken by n+ regions. If we insert n+ regions (narrow stripes) perpendicular to the eddy- current ow we create a blocking p- n- p junction. The layout of the spiral with the eddycurrent blocking structure is shown on Fig. 1.

Fig. 1. Integrated spiral with eddy- current blocking structure.

Fig. 2. The compact model of an integrated spiral. against these currents.
 
 

MEASUREMENT RESULTS

To verify our idea we manufactured identical spirals with and without the blocking structure. We carried out S- parameter measurements on the spirals up to 6 GHz. By circuit optimization we extracted the parameters of the compact equivalent circuit (see Fig. 2). In Table I, the parameters of the spirals are summarized. Fig. 3 shows the quality factor of the spirals versus frequency, where we can see the improvement caused by the eddy- current blocking structure. We observed an increase from 5.3 to 6.0 at 3.5 GHz at an 1.8- nH inductor and from 4.3 to 4.8 at 2.2 GHz at an 2.8- nH inductor.

Fig. 3. Quality factor versus frequency at the measured inductors (see Table I for spiral details).
 

TABLE I SPIRAL PARAMETERS
 

CONCLUSIONS

A new method was introduced to improve the quality factor of the integrated spiral inductors at silicon RF IC’s. The loss reduction is based on blocking the eddy currents in the semiconductive top p+ substrate layer with n+ stripes placed perpendicular to the eddy- current ow. The method was proved by measurements. With the described improvement our fully integrated voltage- controlled oscillator’s (VCO’s) phase noise performance became comparable with the ones having off- chip PCB resonators.

REFERENCES

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[2] J. R. Long and M. A. Copeland, “The modeling, characterization, and design of monolithic inductors for silicon RF IC’s,” IEEE J. Solid- State Circuits, vol. 32, pp. 357– 369, Mar. 1997.
[3] J. Craninckx and M. S. J. Steyaert, “A 1.8 GHz low- phase- noise CMOS VCO using optimized hollow spiral inductors,” IEEE J. Solid- State Circuits, vol. 32, pp. 736– 744, May 1997.
[4] B. Razavi, “Challenges in the design of frequency synthesizers for wireless applications,” in Proc. IEEE Custom Integrated Circuits Conf., 1997, pp. 395– 402.
[5] A. M. Niknejad and R. G. Meyer, “Analysis and optimization of monolithic inductors and transformers for RF IC’s,” IEEE J. Solid- State Circuits, vol. 32, pp. 375– 378, May 1997.
[6] J. Y. C. Chang, A. A. Abidi, and M. Gaitan, “Large suspended inductors on silicon and their use in a 2 um CMOS RF amplifier,” IEEE Electron Device Lett., vol. 14, pp. 246– 248, May 1993.